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1 multiphase pwm regulator for amd fusion? mobile cpus using svi 2.0 ISL62771 the ISL62771 is fully compliant with amd fusion? svi 2.0 and provides a complete solution for microprocessor and graphics processor core power. the ISL62771 controller supports two voltage regulators (vrs) with three integrated gate drivers. the core vr supports 2-, or 1-phase configurations while the northbridge vr supports 1-phase operation. the two vrs share a serial control bus to communicate with the amd cpu and achieve lower cost and smaller board area compared with two-chip solutions. the pwm modulator is based on intersil?s robust ripple regulator (r3) technology?. compared to traditional modulators, the r3 modulator can automatically change switching frequency for faster transient settling ti me during load transients and improved light load efficiency. the ISL62771 has several other key features. both outputs support dcr current sensing with single ntc thermistor for dcr temperature compensation or accurate resistor current sensing. both outputs utilize re mote voltage sense, adjustable switching frequency, oc protection and power-good. applications ? amd fusion cpu/gpu and apu core power ? notebook computers features ? supports amd svi 2.0 serial data bus interface ? dual output controller with integrated drivers ? precision voltage regulation - 0.5% system accuracy over-temperature - 0.5v to 1.55v in 6.25mv steps - enhanced load line accuracy ? supports multiple current sensing methods - lossless inductor dcr current sensing - precision resistor current sensing ? programmable 1- or 2-phase for the core output ? adaptive body diode conduction time reduction ? superior noise immunity and transient response ? output current and voltage telemetry ? differential remote voltage sensing ? high efficiency across entire load range ? programmable vid offset and droop on both outputs ? programmable switching frequency for both outputs ? excellent dynamic current balance between phases ? protection: ocp/woc, ovp, pgood, and thermal monitor ? small footprint 40 ld 5x5 tqfn package - pb-free (rohs compliant) core performance figure 1. efficiency vs load figure 2. v out vs load 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 35 40 45 50 55 i out (a) efficiency (%) v out core = 1.1v v in = 8v v in = 12v v in = 19v 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 1.12 0 5 10 15 20 25 30 35 40 45 50 55 i out (a) v out (a) v in = 8v v in = 12v v in = 19v v out core = 1.1v september 12, 2013 fn8321.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2012, 2013. all rights reserved intersil (and design) and r3 technology are trademarks ow ned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL62771 2 fn8321.2 september 12, 2013 table of contents core performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 simplified application circuit for mid-power cpus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 simplified application circuit for low powe r cpus [1+1 configuration] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 simplified application circuit for low powe r cpus [1+1 configuration] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 gate driver timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 multiphase r3? modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 diode emulation and period stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 channel configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 start-up timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 voltage regulation and load line implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 differential sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 phase current balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 dynamic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 adaptive body diode conduction time reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 resistor configuration options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 vr offset programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ccm switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 amd serial vid interface 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 pre-pwrok metal vid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 svi interface active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 vid-on-the-fly transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 svi data communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 svi bus protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 dynamic load line slope trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 dynamic offset trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 telemetry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 protection features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 current-balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 overvoltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 thermal monitor [ntc, ntc_nb] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 fault recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 interface pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 key component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 inductor dcr current-sensing network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ISL62771 3 fn8321.2 september 12, 2013 resistor current-sensing network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 load line slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 compensator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 current balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 thermal monitor component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 pcb layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
ISL62771 4 fn8321.2 september 12, 2013 simplified application circuit for mid-power cpus figure 3. typical application circuit using dcr sensing ISL62771 isump isumn ph1 ph2 vo1 vo2 gnd pad fb_nb comp_nb vsen_nb vnb_sense vddp pgood isen1 isen2 enable ph1 ph2 vdd ntc_nb imon imon_nb pwrok svt svd p svc vddio ntc vr_hot_l thermal indicator vcore_sense fb comp vsen rtn isump_nb isumn_nb nb_ph vnb ntc ntc cn cn ri ri boot_nb ugate_nb phase_nb lgate_nb vin vnb nb_ph vnb boot2 ugate2 phase2 lgate2 boot1 ugate1 phase1 lgate1 vcore ph2 vo2 vo1 ph1 vin vin pgood_nb
ISL62771 5 fn8321.2 september 12, 2013 simplified application circuit for low power cpus [1+1 configuration] figure 4. typical application circuit using resistor sensing boot_nb ugate_nb phase_nb lgate_nb boot2 ugate2 phase2 lgate2 boot1 ugate1 phase1 lgate1 ISL62771 isump isumn coren gnd pad vddp pgood isen1 isen2 enable vin vin vnb vdd nbn nbp isump_nb isumn_nb nbp nbn +5v open open open open imon imon_nb pwrok svt svd p svc vddio ntc vr_hot thermal indicator fb_nb comp_nb vsen_nb vnb_sense vcore_sense fb comp vsen rtn ntc_nb corep ntc ntc 10k * *resistor required or isen1 will pull high if left open and disable channel 1. cn cn ri ri vcore coren corep pgood_nb
ISL62771 6 fn8321.2 september 12, 2013 simplified application circuit for low power cpus [1+1 configuration] figure 5. typical application circuit using inductor dcr sensing boot_nb ugate_nb phase_nb lgate_nb boot2 ugate2 phase2 lgate2 boot1 ugate1 phase1 lgate1 ISL62771 isump isumn vo gnd pad vddp pgood isen1 isen2 enable vcore vo vin ph vin vnb vdd vnb nb_ph isump_nb isumn_nb nb_ph vnb +5v open open open open imon imon_nb pwrok svt svd p svc vddio ntc vr_hot thermal indicator fb_nb comp_nb vsen_nb vnb_sense vcore_sense fb comp vsen rtn ntc_nb ph ntc ntc 10k * *resistor required or isen1 will pull high if left open and disable channel 1. cn cn ri ri pgood_nb
ISL62771 7 fn8321.2 september 12, 2013 block diagram rtn e/a fb idroop current sense isump isumn comp driver driver lgate1 phase1 ugate1 boot1 vddp ov fault pgood _ + _ + + + driver driver lgate2 phase2 ugate2 boot2 ibal fault oc fault isen2 isen1 current balancing digital interface pwrok svc svd driver driver lgate_nb phase_nb ugate_nb boot_nb ov fault pgood_nb core_i dac1 nb_i dac2 temp monitor ntc_nb ntc vr_hot_l t_monitor offset freq slewrate config enable telemetry d/a a/d idroop idroop_nb rtn 6 e/a fb_nb idroop_nb current sense isump_nb isumn_nb comp_nb vr2 modulator _ + _ + + + vr1 modulator vdd gnd svt oc fault current a/d imon imon_nb vsen vsen_nb vddio core_i nb_i core_v nb_v nb_v voltage a/d core_v voltage a/d
ISL62771 8 fn8321.2 september 12, 2013 pin configuration ISL62771 (40 ld tqfn) top view ntc_nb imon_nb svc vr_hot_l svd vddio svt enable boot2 ugate2 phase2 lgate2 vddp vdd lgate1 phase1 ntc isen2 isen1 isump rtn vsen fb phase_nb lgate_nb pgood_nb comp_nb fb_nb isumn_nb vsen_nb isump_nb comp isumn 1 40 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 pwrok imon pgood ugate1 boot1 ugate_nb boot_nb gnd pad (bottom) pin descriptions pin number symbol description 1 ntc_nb thermistor input to vr_hot_l circuit to monitor northbridge vr temperature. 2 imon_nb northbridge output cu rrent monitor. a current proportional to the northbridge vr output current is sourced from this pin. 3svc serial vid clock input from the cpu processor master device. 4 vr_hot_l thermal indicator signal to amd cpu. therma l overload open drain output indicator active low. 5 svd serial vid data bidirectional signal from the cpu processor master device to the vr. 6 vddio vddio is the processor memory interface power rail an d this pin serves as the reference to the controller ic for this processor i/o signal level. 7 svt serial vid telemetry (svt) data line input to the cpu from the controller ic. telemetry and vid-on-the-fly complete signal provided on from this pin. 8 enable enable input. a high level lo gic on this pin enables both vrs. 9 pwrok system power good input. when this pin is high, the svi 2 interface is active and the i 2 c protocol is running. while this pin is low, the svc and svd in put states determine the pre-pwrok metal vid. this pin must be low prior to the ISL62771 pgood ou tput going high per the amd svi 2.0 controller guidelines. 10 imon core output current monitor. a current proportional to the core vr output current is sourced from this pin. 11 ntc thermistor input to vr_hot_l circuit to monitor core vr temperature. 12 isen2 individual current sensing for channel 2 of the core vr. when isen2 is pulled to +5v, the controller disables channel 2, and the core vr runs in single-phase mode.
ISL62771 9 fn8321.2 september 12, 2013 13 isen1 individual current sensing for channel 1 of the core vr. if isen2 is tied to +5v , this pin cannot be left open and must be tied to gnd with a 10k resistor. if isen1 is tied to +5v , the core portion of the ic is shutdown. 14 isump non-inverting input of the transconductance amplif ier for current monitor and load line of core output. 15 isumn inverting input of the transconductance amplifie r for current monitor and load line of core output. 16 vsen output voltage sense pin for the core controller. connect to the +sense pin of the microprocessor die. 17 rtn output voltage sense return pin for both core vr and northbridge vr . connect to the -sense pin of the microprocessor die. 18 fb output voltage feedback to the inverting input of the core controller error amplifier. 19 comp core controller error amplifier output. a resistor from comp to gnd sets the core vr offset voltage. 20 pgood open-drain output to indicate the core portion of the ic is ready to supply regulated voltage. pull up externally to vdd or 3.3v through a resistor. 21 boot1 connect an mlcc capacitor across the boot1 an d the phase1 pins. the boot capacitor is charged, through an internal boot diode connected from the vddp pin to the boot1 pin, each time the phase1 pin drops below vddp minus the voltage dropped across the internal boot diode. 22 ugate1 output of the phase 1 high-side mosfet gate driv er of the core vr. connect the ugate1 pin to the gate of the phase 1 high-side mosfet(s). 23 phase1 current return path for the phase 1 high-side mosf et gate driver of vr1. connect the phase1 pin to the node consisting of the high-side mo sfet source, the low-side mosfet drain, and the output inductor of phase 1. 24 lgate1 output of the phase 1 low-side mosfet gate driv er of the core vr. connect the lgate1 pin to the gate of the phase 1 low-side mosfet(s). 25 vdd 5v bias power. a resistor [2 ] and a decoupling capacitor should be used from the +5v supply. a high quality, x7r dielectric mlcc capacitor is recommended. 26 vddp input voltage bias for the internal gate drivers. connect +5v to the vddp pin. decouple with at least 1f of capacitance to gnd. a high quality, x7r dielectric mlcc capacitor is recommended. 27 lgate2 output of the phase 2 low-side mosfet gate driv er of the core vr. connect the lgate2 pin to the gate of the phase 2 low-side mosfet(s). 28 phase2 current return path for the phase 2 high-side mo sfet gate driver of the core vr. connect the phase2 pin to the node consisting of the high-side mosfet source, the low-si de mosfet drain, and the output inductor of phase 2. 29 ugate2 output of the phase 2 high-side mosfet gate driv er of the core vr. connect the ugate2 pin to the gate of the phase 2 high-side mosfet(s). 30 boot2 connect an mlcc capacitor across the boot2 and phase2 pins. the boot capacitor is charged, through an internal boot diode connected from the vddp pin to the boot2 pin, each time the phase2 pin drops below vddp minus the voltage dropped across the internal boot diode. 31 boot_nb boot connection of the northbridge vr. conn ect an mlcc capacitor across the boot1_nb and the phase_nb pins. the boot capacitor is charged, through an internal boot diode connected from the vddp pin to the boot_nb pin, each time the phase_nb pin drops below vddp minus the voltage dropped across the internal boot diode. 32 ugate_nb high-side mosfet gate driver of the northbri dge vr. connect the ugate_nb pin to the gate of the high-side mosfet(s) of the northbridge vr. 33 phase_nb phase connection of the northb ridge vr. current return path for the high-side mosfet gate driver of the floating internal driver. connect the phase_nb pin to the node consisting of the high-side mosfet source, the low-side mosfet drain, and the output inductor of the northbridge vr. 34 lgate_nb low-side mosfet gate driver of the northbridge vr. connect the lgate_nb pin to the gate of the low-side mosfet(s) of the northbridge vr. 35 pgood_nb open-drain output to indicate the northbridge portion of the ic is ready to supply regulated voltage. pull-up externally to vddp or 3.3v through a resistor. pin descriptions (continued) pin number symbol description
ISL62771 10 fn8321.2 september 12, 2013 36 comp_nb northbridge vr error amplifie r output. a resistor from comp_nb to gnd sets the northbridge vr offset voltage and is used to set the switching frequency for the core vr and northbridge vr. 37 fb_nb output voltage feedback to the inverting in put of the northbridge controller error amplifier. 38 vsen_nb output voltage sense pin for the northbridge cont roller. connect to the +sense pin of the microprocessor die. 39 isumn_nb inverting input of the transconductance amplifier for current monitor and load line of the northbridge vr. 40 isump_nb non-inverting input of the transconductance amplifier for current monitor and load line of the northbridge vr. gnd (bottom pad) signal common of the ic. al l signals are referenced to the gnd pin. pin descriptions (continued) pin number symbol description ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL62771hrtz 62771 hrtz -10 to +100 40 ld 5x5 tqfn l40.5x5 ISL62771irtz 62771 irtz -40 to +100 40 ld 5x5 tqfn l40.5x5 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL62771 . for more information on msl please see tech brief tb363 .
ISL62771 11 fn8321.2 september 12, 2013 absolute maximum rating s thermal information supply voltage, v dd, v ddp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7v battery voltage, v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28v boot voltage (boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +33v boot to phase voltage (boot-phase) . . . . . . . . . . . . . . . . -0.3v to +7v (dc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +9v(<10ns) phase voltage (phase) . . . . . . . . . . . . . . . . -7v (<20ns pulse width, 10j) ugate voltage (ugate) . . . . . . . . . .phase - 0.3v (dc) to bootphase - 5v . . . . . . . . . . . . . . . . . (<20ns pulse width, 10j) to boot lgate voltage . . . . . . . . . . . . . . . . . . . . . -2.5v (<20ns pulse width, 5j) to vdd + 0.3v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to (vdd + 0.3v) open drain outputs, pgood, pgood_nb, vr_hot_l. . . . . . -0.3v to +7v thermal resistance (typical) ja (c/w) jc (c/w) 40 ld tqfn package (notes 4, 5) . . . . . . . 33 3 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c maximum junction temperature (plastic package) . . . . . . . . . . . .+150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% battery voltage, v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5v to 25v ambient temperature hrtz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +100c irtz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +100c junction temperature hrtz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10c to +125c irtz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications operating conditions: v dd = 5v, t a = -40c to +100c, f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +100c. parameter symbol test conditions min (note 6) typ max (note 6) units input power supply +5v supply current i vdd enable = 1v 8 11 ma enable = 0v 1 a power-on-reset thresholds vdd por threshold vdd_por r v dd rising 4.35 4.5 v vdd_por f v dd falling 4.00 4.15 v system and references system accuracy hrtz %error (v out) no load; closed loop, active mode range, vid = 0.75v to 1.55v, -0.5 +0.5 % vid = 0.25v to 0.74375v -10 +10 mv irtz %error (v out ) no load; closed loop, active mode range, vid = 0.75v to 1.55v -0.8 +0.8 % vid = 0.25v to 0.74375v -12 +12 mv maximum output voltage v out(max) vid = [00000000] 1.55 v minimum output voltage v out(min) vid = [11111111] 0.0 v channel frequency nominal channel frequency f sw(nom) 280 300 320 khz amplifiers current-sense amplifier input offset hrtz i fb = 0a -0.15 +0.15 mv irtz i fb = 0a -0.20 +0.20 mv error amp dc gain a v0 119 db error amp gain-bandwidth product gbw c l = 20pf 17 mhz
ISL62771 12 fn8321.2 september 12, 2013 isen input bias current 20 na power-good (pgood, pgood_nb) and protection monitors pgood low voltage v ol i pgood = 4ma 0.4 v pgood leakage current i oh pgood = 3.3v -1 1 a pwrok high threshold 750 mv vr_hot_l pull-down 11 pwrok leakage current 1 a vr_hot_l leakage current 1 a gate driver ugate pull-up resistance r ugpu 200ma source current 1.0 1.5 ugate source current i ugsrc ugate - phase = 2.5v 2.0 a ugate sink resistance r ugpd 250ma sink current 1.0 1.5 ugate sink current i ugsnk ugate - phase = 2.5v 2.0 a lgate pull-up resistance r lgpu 250ma source current 1.0 1.5 lgate source current i lgsrc lgate - vssp = 2.5v 2.0 a lgate sink resistance r lgpd 250ma sink current 0.5 0.9 lgate sink current i lgsnk lgate - vssp = 2.5v 4.0 a ugate to lgate deadtime t ugflgr ugate falling to lgate rising, no load 23 ns lgate to ugate deadtime t lgfugr lgate falling to ugate rising, no load 28 ns protection overvoltage threshold ov h vsen rising above setpoint for >1s 275 325 375 mv undervoltage threshold ov h vsen falls below setpoint for >1s 275 325 375 mv current imbalance threshold one isen above another isen for >1.2ms 9 mv way overcurrent trip threshold [imonx current based detection] imonx woc all states, i droop = 60ua, r imon = 135k 15 a overcurrent trip threshold [imonx voltage based detection] v imonx_ocp all states, i droop = 45a, i imonx = 11.25a, r imon = 135k 1.485 1.51 1.535 v logic thresholds enable input low v il 1 v enable input high v ih hrtz 1.6 v v ih irtz 1.65 v enable leakage current i enable enable = 0v -1 0 1 a enable = 1v 18 35 a svt impedance 50 svc, svd input low v il % of vddio 30 % svc, svd input high v ih % of vddio 70 % svc, svd leakage enable = 0v, svc, svd = 0v and 1v -1 1 a enable = 1v, svc, svd = 1v -5 1 a enable = 1v, svc, svd = 0v -35 -20 -5 a thermal monitor ntc source current ntc = 0.6v 27 30 33 a ntc thermal warning voltage 600 640 680 mv ntc thermal warning voltage hysteresis 20 mv electrical specifications operating conditions: v dd = 5v, t a = -40c to +100c, f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +100c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units
ISL62771 13 fn8321.2 september 12, 2013 gate driver timing diagram ntc thermal shutdown voltage 530 580 630 mv slew rate vid-on-the-fly slew rate 8 10 12 mv/s soft-start slew rate 10 mv/s note: 6. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. electrical specifications operating conditions: v dd = 5v, t a = -40c to +100c, f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +100c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units pwm ugate lgate 1v 1v t ugflgr t rl t fu t ru t fl t lgfugr
ISL62771 14 fn8321.2 september 12, 2013 theory of operation multiphase r 3 ? modulator the ISL62771 is a multiphase regulator implementing two voltage regulators, core vr and northbridge (nb) vr, on one chip controlled by amd?s? svi2? protocol. the core vr can be programmed for 1- or 2-phase oper ation. the northbridge vr only supports 1-phase operation. both regulators use the intersil patented r 3 ? (robust ripple regulator) modulator. the r 3 ? modulator combines the best fe atures of fixed frequency pwm and hysteretic pwm while eliminat ing many of their shortcomings. figure 6 conceptually shows the multiphase r 3 ? modulator circuit, and figure 7 show s the operation principles. inside the ic, the modulator uses the master clock circuit to generate the clocks for the slave circuits. the modulator discharges the ripple capacitor c rm with a current source equal to g m v o , where g m is a gain factor. c rm voltage v crm is a sawtooth waveform traversing between the vw and comp voltages. it resets to vw when it hits comp, and generates a one-shot master clock signal. a phase sequencer distributes the master clock signal to the slave circuits. in this example, the core vr is in 3-phase mode, the master clock signal is distributed to the three phases, and the clock 1~3 signals will be 120 out-of-phase. if the core vr is in 2-phase mode, the master clock signal is distributed to phases 1 and 2, and the clock1 and clock2 signals will be 180 out- of-phase. if the core vr is in 1-phase mode, the master clock si gnal will be distributed to phase 1 only and be the clock1 signal. each slave circuit has its own ripple capacitor c rs , whose voltage mimics the inductor ripple current. a g m amplifier converts the inductor voltage into a current source to charge and discharge c rs . the slave circuit turns on its pwm pulse upon receiving the clock signal, and the current source charges c rs . when c rs voltage v crs hits vw, the slave circuit turns off the pwm pulse, and the current source discharges c rs . since the controller works with v crs , which are large amplitude and noise-free synthesized signals, it achieves lower phase jitter than conventional hysteretic mode and fixed pwm mode controllers. unlike conventional hysteretic mode converters, the error amplifier allows the ISL62771 to maintain a 0.5% output voltage accuracy. figure 8 shows the operation principles during load insertion response. the comp voltage ri ses during load insertion, generating the master clock sign al more quickly, so the pwm pulses turn on earlier, increasing the effective switching frequency. this allows for higher control loop bandwidth than conventional fixed frequency pwm controllers. the vw voltage rises as the comp voltage rises, making the pwm pulses wider. during load release response, th e comp voltage falls. it takes the master clock circuit longer to generate the next master clock signal so the pwm pulse is held off until needed. the vw voltage falls as the comp voltage falls, reducing the current pwm pulse width. this kind of behavior gives the ISL62771 excellent response speed. the fact that all the phases share the same vw window voltage, also ensures excellent dynamic current balance among phases. figure 6. r 3 ? modulator circuit crm gmvo master clock vw comp master clock phase sequencer clock1 clock2 r i l1 gm clock1 phase1 crs1 vw s q pwm1 l1 r i l2 gm clock2 phase2 crs2 vw s q pwm2 l2 co vo vcrm vcrs1 vcrs2 master clock circuit slave circuit 1 slave circuit 2 r i l3 gm clock3 phase3 crs3 vw s q pwm3 l3 vcrs3 slave circuit 3 clock3 figure 7. r 3 ? modulator operation principles in steady state comp vcrm master clock pwm1 vw clock1 pwm2 clock2 hysteretic window pwm3 vcrs3 clock3 vcrs2 vcrs1 vw
ISL62771 15 fn8321.2 september 12, 2013 diode emulation and period stretching the ISL62771 can operate in diode emulation (de) mode to improve light-load efficiency. in de mode, the low-side mosfet conducts when the current is flowing from source-to-drain and does not allow reverse current, th us emulating a diode. figure 9 shows that when lgate is on, the low-side mosfet carries current, creating negative voltage on th e phase node due to the voltage drop across the on-resistance. th e ISL62771 monitors the current by monitoring the phase node voltage. it turns off lgate when the phase node voltage reaches zero to prevent the inductor current from reversing the direction and creating unnecessary power loss. if the load current is light enou gh (see figure 9), the inductor current reaches and stays at zero before the next phase node pulse, and the regulator is in discontinuous conduction mode (dcm). if the load current is heavy enough, the inductor current will never reach 0a, and the regulator is in ccm, although the controller is in de mode. figure 10 shows the operation principle in diode emulation mode at light load. the load gets increm entally lighter in the three cases from top to bottom. the pwm on-time is determined by the vw window size and therefore is the same, making the inductor current triangle the same in the three cases. the ISL62771 clamps the ripple capacitor voltage v crs in de mode to make it mimic the inductor current. it takes the comp voltage longer to hit v crs , naturally stretching the switching period. the inductor current triangles move farther apart such that the inductor current average value is equal to the load current. the reduced switching frequency helps increase light-load efficiency. channel configuration individual pwm channels of the core vr can be disabled by connecting the isenx pin of the channel not required to +5v. for example, placing the controller in a 1+1 configuration (see figure 5) requires isen2 of the core vr to be tied to +5v. this disables channel 2 of the core vr . isen1 must be tied through a 10k resistor to gnd to prevent this pin from pulling high and disabling the channel. connecting isen1 to +5v will disable the core vr output. power-on reset before the controller has suffic ient bias to guarantee proper operation, the ISL62771 requires a +5v input supply tied to vdd and vddp to exceed the vdd rising power-on reset (por) threshold. once this threshold is reached or exceeded, the ISL62771 has enough bias to check the state of the svi inputs once enable is taken high. hysteresis between the rising and the falling thresholds assure the ISL62771 does not inadvertently turn off unless the bias voltage drops substantially (see ?electrical specifications? on page 11). note that vin must be present for the controller to drive the output voltage. figure 8. r 3 ? modulator operation principles in load insertion response comp v crm master clock pwm1 vcrs1 vw clock1 pwm2 vcrs2 clock2 pwm3 clock3 vcrs3 vw ugate phase il lgate figure 9. diode emulation il il v crs il v crs v crs vw ccm / dcm boundary light dcm deep dcm vw vw figure 10. period stretching
ISL62771 16 fn8321.2 september 12, 2013 start-up timing with the controller's vdd por threshold exceeded and vin voltage present, the start-up sequence begins when enable exceeds the logic high threshold. figure 12 shows the typical start-up timing of core and northbridge vrs. the ISL62771 uses a digital soft-start to ramp-up the dac to the voltag e programmed by the metal vid. pgood is asserted high at the en d of the ramp up. similar results occur if enable is tied to vdd, with the soft-start sequence starting 8ms after vdd crosses the por threshold. voltage regulation and load line implementation after the soft-start sequence, th e ISL62771 regulates the output voltages to the pre-pwrok metal vid programmed, see table 5. the ISL62771 controls the no-load output voltage to an accuracy of 0.5% over the range of 0.75v to 1.55v. a differential amplifier allows voltage sensing for precise voltage regulation at the microprocessor die. vdd svc svd enable pwrok v core / v core_nb 1 7 8 figure 11. svi interface timing diagram: typical pre-pwrok metal vid start-up pgood & pgood_nb 3 4 2 5 6 metal_vid v_svi interval 1 to 2: ISL62771 waits to por. interval 2 to 3: svc and svd are externally set to pre-metal vid code. interval 3 to 4: enable locks pre-metal vid c ode. both outputs soft-start to this level. interval 4 to 5: pgood signal goes high, indicating proper operation. interval 6 to 7: svc and svd data lines communicate change in vid code. interval 7 to 8: ISL62771 responds to vid-on-the-fly code change and issues a votf for positive vid changes. interval 5 to 6: pgood and pgood_nb high is detected and pwrok is taken high. the ISL62771 is prepared for svi commands. svt telemetry telemetry votf post 8: telemetry is clocked out of the ISL62771. vdd enable dac 8ms metalvid slew rate vid command voltage pgood pwrok vin figure 12. typical soft-start waveforms figure 13. differential sensing and load line implementation x 1 e/a dac svid[7:0] r droop i droop vdac v droop fb comp vcc sense vss sense rtn vss internal to ic ?catch? resistor ?catch? resistor vr local vo + - +- + + - svc svd
ISL62771 17 fn8321.2 september 12, 2013 as the load current increases from zero, the output voltage droops from the vid programmed value by an amount proportional to the load current, to achieve the load line. the ISL62771 can sense the inductor current through the intrinsic dc resistance (dcr) of the inductors, as shown in figures 3 and 5, or through resist ors in series with the inductors as shown in figure 4. in both methods, capacitor c n voltage represents the total inductor current. an amplifier converts c n voltage into an internal current source with the gain set by resistor r i , see equation 1. this isum current is used for load line implementation, current monitoring on the imon pins and overcurrent protection. figure 13 shows the load-line implementation. the ISL62771 drives a current source (i droop ) out of the fb pin, as described by equation 2. when using inductor dcr current sensing, a single ntc element is used to compensate the positive temperature coefficient of the copper winding, thus sustaining the load-line accuracy with reduced cost. i droop flows through resistor r droop and creates a voltage drop as shown in equation 3. v droop is the droop voltage required to implement load line. changing r droop or scaling i droop can change the load line slope. since i sum sets the overcurrent protection level, it is recommended to first scale i sum based on ocp requirement, then select an appropriate r droop value to obtain the desired load line slope. differential sensing figure 13 also shows the differential voltage sensing scheme. vcc sense and vss sense are the remote voltage sensing signals from the processor die. a unity ga in differential amplifier senses the vss sense voltage and adds it to the dac output. the error amplifier regulates the inverting and non-inverting input voltages to be equal as shown in equation 4: rewriting equation 4 and substituting equation 3 gives equation 5. the exact equation required for load-line implementation. the vcc sense and vss sense signals come from the processor die. the feedback is an open circuit in the absence of the processor. as figure 13 shows, it is recommended to add a ?catch? resistor to feed the vr local output voltage back to the compensator, and to add another ?catch? resistor to connect the vr local output ground to the rtn pin. these resistors, typically 10 ~100 , provide voltage feedback if the system is powered up without a processor installed. phase current balancing the ISL62771 monitors individual phase average current by monitoring the isen1 and isen2 voltages. figure 14 shows the recommended current balancing circuit for dcr sensing. each phase node voltage is averaged by a low-pass filter consisting of r isen and c isen , and is presented to the corresponding isen pin. r isen should be routed to the inductor phase-node pad in order to eliminate the effect of phase node parasitic pcb dcr. equations 6 through 7 give the isen pin voltages: where r dcr1 and r dcr2 are inductor dcr; r pcb1 and r pcb2 are parasitic pcb dcr between the inductor output side pad and the output voltage rail; and i l1 and i l2 are inductor average currents. the ISL62771 adjusts the phase pulse-width relative to the other phases to make v isen1 =v isen2 , thus to achieve i l1 =i l2 , when r dcr1 =r dcr2 and r pcb1 =r pcb2 . using the same components for l1 and l2 provides a good match of r dcr1 and r dcr2 . board layout determines r pcb1 and r pcb2 . it is recommended to have a symmetrical layout for the power delivery path between each inductor and the output voltage rail, such that r pcb1 =r pcb2 . sometimes, it is difficult to implement symmetrical layout. for the circuit shown in figure 14, asymmetric layout causes different r pcb1 and r pcb2 values, thus creating a current imbalance. figure 15 shows a differential sensing current i sum v cn r i ---------- - = (eq. 1) i droop 5 4 -- - xi sum 5 4 -- - x v cn r i ---------- - == (eq. 2) v droop r droop i droop = (eq. 3) vcc sense v + droop v dac vss sense + = (eq. 4) vcc sense vss sense ? v dac r droop i droop ? = (eq. 5) figure 14. current balancing circuit internal to ic v o isen2 r isen c isen isen1 r isen c isen l2 l1 r dcr2 r dcr1 phase2 phase1 i l2 i l1 r pcb2 r pcb1 v isen1 r dcr1 r pcb1 + () i l1 = (eq. 6) v isen2 r dcr2 r pcb2 + () i l2 = (eq. 7) internal to ic v o isen2 r isen c isen isen1 r isen c isen l2 l1 r dcr2 r dcr1 phase2 phase1 i l2 i l1 r pcb2 r pcb1 r isen r isen r isen r isen v2p v 2n v1p v 1n figure 15. differential-sensing current balancing circuit
ISL62771 18 fn8321.2 september 12, 2013 balancing circuit recommended for ISL62771. the current sensing traces should be routed to the inductor pads so they only pick up the inductor dcr voltage. each isen pin sees the average voltage of two sources: its own, phase inductor phase-node pad, and the other phase inductor output side pad. equations 8 through 9 give the isen pin voltages: the ISL62771 will make v isen1 = v isen2 as shown in equation 10: rewriting equation 10 gives equation 11: therefore: current balancing (i l1 =i l2 ) is achieved when r dcr1 =r dcr2 . r pcb1 and r pcb2 do not have any effect. since the slave ripple capacitor voltages mimic the inductor currents, the r 3 ? modulator can naturally achieve excellent current balancing during steady state and dynamic operations. figure 16 shows the current balancing performance of the evaluation board with load transi ent of 12a/51a at different rep rates. the inductor currents follow the load current dynamic change with the output capacitors supplying the difference. the inductor currents can track the load current well at a low repetition rate, but cannot keep up when the repetition rate gets into the hundred-khz range, where it is out of the control loop bandwidth. the controller achieves excellent current balancing in all cases installed. v isen1 v 1p v 2n + = (eq. 8) v isen2 v 1n v 2p + = (eq. 9) v 1p v 2n + v 1n v 2p + = (eq. 10) v 1p v 1n ? v 2p v 2n ? = (eq. 11) r dcr1 i l1 r dcr2 i l2 = (eq. 12) figure 16. current balancing during dynamic operation. ch1: i l1 , ch2: i load , ch3: i l2 , ch4: i l3 rep rate = 10khz rep rate = 25khz rep rate = 50khz rep rate = 100khz rep rate = 200khz
ISL62771 19 fn8321.2 september 12, 2013 modes of operation the core vr can be configured for 2- or 1-phase operation. table 1 shows core vr configur ations and operational modes, programmed by the isen2 pin status and the psl0_l & psl1_l commands via the svi 2 interface, see table 9. for a 1-phase configuration, tie the isen2 pin to 5v. in this configuration, only phase 1 is active. for 2-phase configurations, the core vr operates in 2-phase ccm with psi0_l and psi_l both high. if psi0_l is taken low via the svi 2 interface, the core vr sheds phase 2 and the core vr enters 1-phase de mode. when both psi0_l and psi1_l are taken low, the core vr continues to operate in the 1-phase de mode. in a 1-phase configuration, the core vr operates in 1-phase ccm and enters 1-phase de when psi0_l is taken low and continues to operate in this mode when both psi0_l and psi1_l are taken low. the core vr can be disabled completely by connecting isen1 to +5v. ISL62771 northbridge vr operates in 1-phase ccm. table 2 shows the northbridge vr operational modes, which are programmed by the psi0_l an d psi1_l bits of the svi 2 command. the northbridge vr operates in 1-phase ccm and enters 1-phase de when psi0_l goes low and remains in this mode of operation when both psi0_l and psi1_l are low. the core and northbridge vrs have an overcurrent threshold of 1.5v on imon and imon_nb respectively and this level does not vary based on channel configuration. see ?overcurrent? on page 25 for more details. dynamic operation core vr and northbridge vr be have the same during dynamic operation. the controller responds to vid-on-the-fly changes by slewing to the new voltage at a fixed slew rate. during negative vid transitions, the output voltage decays to the lower vid value at the slew rate determined by the load. the r 3 ? modulator intrinsically has voltage feed-forward. the output voltage is insensitive to a fast slew rate input voltage change. adaptive body diode conduction time reduction in dcm, the controller turns off the low-side mosfet when the inductor current approaches zero. during on-time of the low-side mosfet, phase voltage is negative, and the amount is the mosfet r ds(on) voltage drop, which is proportional to the inductor current. a phase comp arator inside the controller monitors the phase voltage during on-time of the low-side mosfet and compares it with a threshold to determine the zero crossing point of the inductor current. if the inductor current has not reached zero when the low-side mosfet turns off, it will flow through the low-side mosfet bo dy diode, causing the phase node to have a larger voltage drop until it decays to zero. if the inductor current has crossed zero and reversed the direction when the low-side mosfet turns off, it will flow through the high-side mosfet body diode, causing the phase node to have a spike until it decays to zero. th e controller continues monitoring the phase voltage after turning off the low-side mosfet. to minimize the body diode-related loss, the controller also adjusts the phase comparator threshold vo ltage accordingly in iterative steps such that the low-side mosfet body diode conducts for approximately 40ns. resistor configuration options the ISL62771 uses the comp and comp_nb pins to configure some functionality within the ic. resistors from these pins to gnd are read during the first portion of the soft-start sequence. the following sections outline how to se lect the resistor values for each of these pins to correctly program the output voltage offset of each output and switching frequency used for both vrs. vr offset programming a positive or negative offset is programmed for the core vr using a resistor to ground from the co mp pin and the northbridge in a similar manner from the comp_n b pin. table 3 provides the resistor value to select the desired output voltage offset. the 1% tolerance resistor value shown in the table must be used to program the corresponding core or nb output voltage offset. the min and max tolerance values provide margin to insure the 1% tolerance resistor will be read correctly. table 1. core vr modes of operation config. isen2 psl0_l & psi1_l mode imon ocp threshold (v) 2-phase core vr config. to power stage 11 2-phase ccm 1.5 01 1-phase de 00 1-phase de 1-phase core vr config. tied to 5v 11 1-phase ccm 1.5 01 1-phase de 00 1-phase de table 2. northbridge vr modes of operation config. psl0_l and psi1_l mode imon ocp threshold 1-phase nb vr config. 11 1-phase ccm 1.5v 01 1-phase de 00 1-phase de table 3. comp and comp_nb output voltage offset selection resistor value [ k ] comp v core offset [mv] comp_nb offset [mv] min tolerance 1% tolerance value max tolerance 5.54 5.62 5.70 -43.75 18.75 7.76 7.87 7.98 -37.5 31 .25 11.33 11.5 11.67 -31.25 43.76 16.65 16.9 17.15 -25 50
ISL62771 20 fn8321.2 september 12, 2013 ccm switching frequency the core and northbridge vr switching frequency is set by the programming resistor on comp_nb. when the ISL62771 is in continuous conduction mode (ccm), the switching frequency is not absolutely constant due to the nature of the r 3 ? modulator. as explained in the ?multiphase r3? modulator? on page 14, the effective switching frequency incr eases during load insertion and decreases during load release to achieve fast response. thus, the switching frequency is relatively constant at steady state. variation is expected when the power stage condition, such as input voltage, output voltage, load, etc. changes. the variation is usually less than 10% and does not have any significant effect on output voltage ripple magnitude. table 4 defines the switching frequency based on the resistor value used to program the comp_nb pin. use the previous table related to comp_nb to determine the correct resistor value in these ranges to program the desired output offset and switching frequency configuration. the controller monitors svi commands to determine when to enter power-saving mode, implement dynamic vid changes, and shut down individual outputs. amd serial vid interface 2.0 the on-board serial vid interface 2.0 (svi 2) circuitry allows the amd processor to directly control the core and northbridge voltage reference levels within the ISL62771. once the pwrok signal goes high, the ic begins monitoring the svc and svd pins for instructions. the ISL62771 uses a digital-to-analog converter (dac) to generate a reference voltage based on the decoded svi value. see figure 11 for a simple svi interface timing diagram. pre-pwrok metal vid typical motherboard start-up begi ns with the controller decoding the svc and svd inputs to determine the pre-pwrok metal vid setting (see table 5). once the enable input exceeds the rising threshold, the ISL62771 decodes and locks the decoded value into an on-board hold register. the internal dac circuitry begins to ramp core and northbridge vrs to the decoded pre-pwrok metal vid output level. the digital soft-start circuitry ramps the internal reference to the target gradually at a fixed rate of 10mv/s. the controlled ramp of all output voltage planes reduces in-rush current during the soft-start interval. at the end of the soft-start interval, the pgood and pgood_nb outputs transition high, indicating both output planes are within regulation limits. if the enable input falls below th e enable falling threshold, the ISL62771 tri-states both outputs. pgood and pgood_nb are pulled low with the loss of enable. the core and northbridge vr output voltages decay, based on output capacitance and load leakage resistance. if bias to vdd falls below the por level, the ISL62771 responds in the manner previously described. once vdd and enable rise above their respective rising thresholds, the internal dac circuitry re-acquires a pre-pwrok metal vid code, and the controller soft-starts. svi interface active once the core and northbri dge vrs have successfully soft-started and pgood and pgoo d_nb signals transition high, pwrok can be asserted externally to the ISL62771. once pwrok is asserted to the ic, sv i instructions can begin as the controller actively monitors the svi interface. details of the svi bus protocol are provided in th e ?amd serial vid interface 2.0 (svi2) specification?. see amd publication #48022. once a vid change command is received, the ISL62771 decodes the information to determine whic h vr is affected and the vid target is determined by the byte combinations in table 6. the internal dac circuitry steps the output voltage of the vr commanded to the new vid level. during this time, one or more of the vr outputs could be targeted. in the event either vr is commanded to power-off by serial vid commands, the pgood signal remains asserted. if the pwrok input is de-asserted , then the controller steps both the core and the northbridge vrs back to the stored pre-pwrok metal vid level in the holding register from initial soft-start. no attempt is made to read the svc and svd inputs during this time. if pwrok is re-asserted, then the ISL62771 svi interface waits for instructions. 19.3 19.6 19.89 -18.75 37.5 24.53 24.9 25.27 -12.5 25 33.49 34.0 34.51 -6.25 12.5 40.58 41.2 41.81 6.25 0 51.52 52.3 53.08 18.75 18.75 72.10 73.2 74.29 31.25 31.25 93.87 95.3 96.72 43.76 43.76 119.19 121 112.81 50 50 151.69 154 156.31 37.5 37.5 179.27 182 184.73 25 25 206.85 210 213.15 12.5 12.5 open 0 0 table 4. switching frequency selection frequency [khz] comp_nb range [k ] 300 57.6 to open 400 5.62 to 41.2 table 3. comp and comp_nb output voltage offset selection (continued) resistor value [ k ] comp v core offset [mv] comp_nb offset [mv] min tolerance 1% tolerance value max tolerance table 5. pre-pwrok metal vid codes svc svd output voltage (v) 00 1.1 01 1.0 1 0 0.9 1 1 0.8
ISL62771 21 fn8321.2 september 12, 2013 if enable goes low during no rmal operation, all external mosfets are tri-stated and both pgood and pgood_nb are pulled low. this event clears the pre-pwrok metal vid code and forces the controller to check svc and svd upon restart, storing the pre-pwrok metal vid code found on restart. a por event on vcc during normal operation shuts down both regulators, and both pgood outputs are pulled low. the pre-pwrok metal vid code is not retained. loss of vin during operation will typically cause the controller to enter a fault condition on one or both outputs. the controller will shut down both core and northbridge vrs and latch off. the pre-pwrok metal vid code is not retained during the process of cycling enable to reset the fault latch and restart the controller. vid-on-the-fly transition once pwrok is high, the ISL62771 detects this flag and begins monitoring the svc and svd pins for svi instructions. the microprocessor follows the protocol outlined in the following sections to send instructions for vid-on-the-fly transitions. the ISL62771 decodes the instruction and acknowledges the new vid code. for vid codes higher than the current vid level, the ISL62771 begins stepping the commanded vr outputs to the new vid target at the fixed slew rate of 10mv/s. once the dac ramps to the new vid code, a vid-on-the-fly complete (votfc) request is sent on the svi lines. when the vid codes are lower than the current vid level, the ISL62771 checks the state of power state bits in the svi command. if power state bits are no t active, the controller begins stepping the regulator output to the new vid target. if the power state bits are active, the controll er allows the output voltage to decay and slowly steps the dac down with the natural decay of the output. this allows the controller to quickly recover and move to a high vid code if commanded. the controller issues a votfc request on the svi lines once the svi command is decoded and prior to reaching the final output voltage. votfc requests do not take priority over telemetry per the amd svi 2 specification. svi data communication protocol the svi wire protocol is based on the i 2 c bus concept. three wires [serial clock (svc) and serial data (svd) and telemetry (svt)], carry information betwee n the amd processor (master) and vr controller (slave) on the bus. the master initiates and terminates svi transactions and drives the clock, svc, during a transaction. the amd processor is always the master, and the voltage regulators are the slaves. the slave receives the svi transactions and acts accordingl y. mobile svi wire protocol timing is based on high-speed mode i 2 c. see amd publication #48022 for additional details.
ISL62771 22 fn8321.2 september 12, 2013 . table 6. serial vid codes svid[7:0]voltage (v)svid[7:0]voltage (v)svid[7:0]voltage (v)svid[7:0]voltage (v) 0000_0000 1.55000 0010_0000 1.35000 0100_0000 1.15000 0110_0000 0.95000 0000_0001 1.54375 0010_0001 1.34375 0100_0001 1.14375 0110_0001 0.94375 0000_0010 1.53750 0010_0010 1.33750 0100_0010 1.13750 0110_0010 0.93750 0000_0011 1.53125 0010_0011 1.33125 0100_0011 1.13125 0110_0011 0.93125 0000_0100 1.52500 0010_0100 1.32500 0100_0100 1.12500 0110_0100 0.92500 0000_0101 1.51875 0010_0101 1.31875 0100_0101 1.11875 0110_0101 0.91875 0000_0110 1.51250 0010_0110 1.31250 0100_0110 1.11250 0110_0110 0.91250 0000_0111 1.50625 0010_0111 1.30625 0100_0111 1.10625 0110_0111 0.90625 0000_1000 1.50000 0010_1000 1.30000 0100_1000 1.10000 0110_1000 0.90000 0000_1001 1.49375 0010_1001 1.29375 0100_1001 1.09375 0110_1001 0.89375 0000_1010 1.48750 0010_1010 1.28750 0100_1010 1.08750 0110_1010 0.88750 0000_1011 1.48125 0010_1011 1.28125 0100_1011 1.08125 0110_1011 0.88125 0000_1100 1.47500 0010_1100 1.27500 0100_1100 1.07500 0110_1100 0.87500 0000_1101 1.46875 0010_1101 1.26875 0100_1101 1.06875 0110_1101 0.86875 0000_1110 1.46250 0010_1110 1.26250 0100_1110 1.06250 0110_1110 0.86250 0000_1111 1.45625 0010_1111 1.25625 0100_1111 1.05625 0110_1111 0.85625 0001_0000 1.45000 0011_0000 1.25000 0101_0000 1.05000 0111_0000 0.85000 0001_0001 1.44375 0011_0001 1.24375 0101_0001 1.04375 0111_0001 0.84375 0001_0010 1.43750 0011_0010 1.23750 0101_0010 1.03750 0111_0010 0.83750 0001_0011 1.43125 0011_0011 1.23125 0101_0011 1.03125 0111_0011 0.83125 0001_0100 1.42500 0011_0100 1.22500 0101_0100 1.02500 0111_0100 0.82500 0001_0101 1.41875 0011_0101 1.21875 0101_0101 1.01875 0111_0101 0.81875 0001_0110 1.41250 0011_0110 1.21250 0101_0110 1.01250 0111_0110 0.81250 0001_0111 1.40625 0011_0111 1.20625 0101_0111 1.00625 0111_0111 0.80625 0001_1000 1.40000 0011_1000 1.20000 0101_1000 1.00000 0111_1000 0.80000 0001_1001 1.39375 0011_1001 1.19375 0101_1001 0.99375 0111_1001 0.79375 0001_1010 1.38750 0011_1010 1.18750 0101_1010 0.98750 0111_1010 0.78750 0001_1011 1.38125 0011_1011 1.18125 0101_1011 0.98125 0111_1011 0.78125 0001_1100 1.37500 0011_1100 1.17500 0101_1100 0.97500 0111_1100 0.77500 0001_1101 1.36875 0011_1101 1.16875 0101_1101 0.96875 0111_1101 0.76875 0001_1110 1.36250 0011_1110 1.16250 0101_1110 0.96250 0111_1110 0.76250 0001_1111 1.35625 0011_1111 1.15625 0101_1111 0.95625 0111_1111 0.75625 note: *indicates a vid not required for amd family 10h processors.
ISL62771 23 fn8321.2 september 12, 2013 svi bus protocol table 7. serial vid codes svid[7:0]voltage (v)svid[7:0]voltage (v)svid[7:0]voltage (v)svid[7:0]voltage (v) 1000_0000 0.75000 1010_0000 0.55000* 1100_0000 0.35000* 1110_0000 0.15000* 1000_0001 0.74375 1010_0001 0.54375* 1100_0001 0.34375* 1110_0001 0.14375* 1000_0010 0.73750 1010_0010 0.53750* 1100_0010 0.33750* 1110_0010 0.13750* 1000_0011 0.73125 1010_0011 0.53125* 1100_0011 0.33125* 1110_0011 0.13125* 1000_0100 0.72500 1010_0100 0.52500* 1100_0100 0.32500* 1110_0100 0.12500* 1000_0101 0.71875 1010_0101 0.51875* 1100_0101 0.31875* 1110_0101 0.11875* 1000_0110 0.71250 1010_0110 0.51250* 1100_0110 0.31250* 1110_0110 0.11250* 1000_0111 0.70625 1010_0111 0.50625* 1100_0111 0.30625* 1110_0111 0.10625* 1000_1000 0.70000 1010_1000 0.50000* 1100_1000 0.30000* 1110_1000 0.10000* 1000_1001 0.69375 1010_1001 0.49375* 1100_1001 0.29375* 1110_1001 0.09375* 1000_1010 0.68750 1010_1010 0.48750* 1100_1010 0.28750* 1110_1010 0.08750* 1000_1011 0.68125 1010_1011 0.48125* 1100_1011 0.28125* 1110_1011 0.08125* 1000_1100 0.67500 1010_1100 0.47500* 1100_1100 0.27500* 1110_1100 0.07500* 1000_1101 0.66875 1010_1101 0.46875* 1100_1101 0.26875* 1110_1101 0.06875* 1000_1110 0.66250 1010_1110 0.46250* 1100_1110 0.26250* 1110_1110 0.06250* 1000_1111 0.65625 1010_1111 0.45625* 1100_1111 0.25625* 1110_1111 0.05625* 1001_0000 0.65000 1011_0000 0.45000* 1101_0000 0.25000* 1111_0000 0.05000* 1001_0001 0.64375 1011_0001 0.44375* 1101_0001 0.24375* 1111_0001 0.04375* 1001_0010 0.63750 1011_0010 0.43750* 1101_0010 0.23750* 1111_0010 0.03750* 1001_0011 0.63125 1011_0011 0.43125* 1101_0011 0.23125* 1111_0011 0.03125* 1001_0100 0.62500 1011_0100 0.42500* 1101_0100 0.22500* 1111_0100 0.02500* 1001_0101 0.61875 1011_0101 0.41875* 1101_0101 0.21875* 1111_0101 0.01875* 1001_0110 0.61250 1011_0110 0.41250* 1101_0110 0.21250* 1111_0110 0.01250* 1001_0111 0.60625 1011_0111 0.40625* 1101_0111* 0.20625* 1111_0111 0.00625* 1001_1000 0.60000* 1011_1000 0.40000* 1101_1000 0.20000* 1111_1000 off* 1001_1001 0.59375* 1011_1001 0.39375* 1101_1001 0.19375* 1111_1001 off* 1001_1010 0.58750* 1011_1010 0.38750* 1101_1010 0.18750* 1111_1010 off* 1001_1011 0.58125* 1011_1011 0.38125* 1101_1011 0.18125* 1111_1011 off* 1001_1100 0.57500* 1011_1100 0.37500* 1101_1100 0.17500* 1111_1100 off* 1001_1101 0.56875* 1011_1101 0.36875* 1101_1101 0.16875* 1111_1101 off* 1001_1110 0.56250* 1011_1110 0.36250* 1101_1110 0.16250* 1111_1110 off* 1001_1111 0.55625* 1011_1111 0.35625* 1101_1111 0.15625* 1111_1111 off* note: *loosened amd requirements at these levels. figure 17. svd packet structure 1 23 4 567 12 14 15 16 17 13 10 svd svc start psi1_l vid bits [7:1] 11 8 9 18 19 20 21 22 23 24 25 26 27 vid bit [0] psi0_l ack ack ack
ISL62771 24 fn8321.2 september 12, 2013 the amd processor bus protocol is compliant with smbus send byte protocol for vid transactions. the amd svd packet structure is shown in figure 17. the description of what each bit of the three bytes that make up the sv i command are shown in table 8. during a transaction, the proc essor sends the start sequence followed by each of the three bytes, which end with an optional acknowledge bit. the ISL62771 does not drive the svd line during the ack bit. finally, the processor sends the stop sequence. after the ISL62771 has detected the stop, it can then proceed with the commanded action from the transaction. power states svi2 defines two power state indicator levels, see table 9. as processor current consumption re duces the power state indicator level changes to improve vr efficiency under low power conditions. for the core vr operating in 2-phase mode, when psi0_l is asserted, channel 2 is tri-stated and channel 1 enters diode emulation mode to boost efficiency. when psi0_l and psi1_l are asserted low, the core vr continues to operate in this mode. for the 1-phase northbridge vr, when psi0_l is asserted, channel 1 enters diode emulation mode to boost efficiency. when psi0_l and psi1_l are asserted low, the northbridge vr continues to operate in this fashion. it is possible for the processor to assert or deassert psi0_l and psi1_l out of order. psi0_l takes priority over ps i1_l. if psi0_l is deasserted while psi1_l is still asserted, the ISL62771 will return the selected vr back full channel ccm operation. dynamic load line slope trim the ISL62771 supports the svi2 ability for the processor to manipulate the load line slope of the core and northbridge vrs independently using the serial vid interface. the slope manipulation applies to the initial load line slope. a load line slope trim will typically coincide with a votf change. see table 10 for more information about the load line slope trim feature of the ISL62771. dynamic offset trim the ISL62771 supports the svi2 ability for the processor to manipulate the output voltage offset of the core and northbridge vrs. this offset is in addition to any output voltage offset set via the comp resistor reader. the dy namic offset trim can disable the comp resistor programmed of fset of either output when ?disable all offset? is selected. table 8. svd data packet bits description 1:5 always 11000b 6 core domain selector bit, if se t then the following data byte contains vid, power state, telemetry control, load line trim and offset trim apply to the core vr. 7 northbridge domain selector bit, if set then the following data byte contains vid, power state, telemetry control, load line trim and offset trim apply to the northbridge vr. 8always 0b 9acknowledge bit 10 psi0_l 11:17 vid code bits [7:1] 18 acknowledge bit 19 vid code bit [0] 20 psi1_l 21 tfn (telemetry functionality) 22:24 load line slope trim 25:26 offset trim [1:0] 27 acknowledge bit table 9. psi0_l, psi1_l and tfn definition function bit description psi0_l 10 power state indicate level 0. when this signal is asserted (active low) the processor is in a low enough power state for the vr controller to take action to boost efficiency by dropping phases and/or entering 1-phase de. psi1_l 20 power state indicate level 1. when this signal is asserted (active low) the processor is in a low enough power state for the vr controller to take action to boost efficiency by dropping phases and entering 1-phase de tfn 21 telemetry functionality. this is an active high signal that allows the processor to control the telemetry functionality of the vr. table 10. load line slope trim definition load line slope trim [2:0] description 000 disable ll 001 -40% m change 010 -20% m change 011 no change 100 +20% m change 101 +40% m change 110 +60% m change 111 +80% m change table 11. offset trim definition offset trim [1:0] description 00 disable all offset 01 -25mv change 10 0mv change 11 +25mv change
ISL62771 25 fn8321.2 september 12, 2013 telemetry the ISL62771 can provide volt age and current information through the telemetry system outlined by the amd svi2 specification. the telemetry data is transmitted through the svc and svt lines of the svi 2 interface. current telemetry is based on a voltage generated across a 133k resistor placed from the im on pin to gnd. the current flowing out of the imon pin is proportional to the load current in the vr. the i sum current defined in the ?voltage regulation and load line implementation? on page 16 provides the base conversion from the load current to the internal amplifier created i sum current. the i sum current is then divided down by a factor of 4 to create the imon current, which flows out of the imon pin. the i sum current will measure 35a when the load current is at full load based on a droop current designed for 45a at the same load current. the difference between the i sum current and the droop current is provided in equation 2. the imon current will measure 11.25a at full load cu rrent for the vr and the imon voltage will be 1.2v. the load percentage, which is reported by the ic is based on this voltage. when the load is 25% of the full load, the voltage on the imon pin will be 25% of 1.2v or 0.3v. the svi interface allows the selection of no telemetry, voltage only, or voltage and current telemetry on either or both of the vr outputs. the tfn bit along with the core and northbridge domain selector bits are used by the processor to change the functionality of telemetry, see table 12 for more information. protection features core vr and northbridge vr both provide overcurrent, current-balance, undervoltage, an d overvoltage fault protections. the controller also provides ov er-temperature protection. the following discussion is based on core vr and also applies to the northbridge vr. overcurrent the imon voltage provides a means of determining the load current at any moment in time. the overcurrent protection (ocp) circuitry monitors the imon voltage to determine when a fault occurs. based on the previous description in the?voltage regulation and load line implementation? on page 16, the current, which flows out of the imon pin is proportional to the isum current. the isum current is created from the sensed voltage across cn which is a measure of the load current based upon the sensing element selected. the imon current is generated internally and is 1/4 of the isum current. the edc or idd spike current value for the amd cpu load is used to set the maximum current level for droop and the imon voltage of 1.2v, which indicates 100% loading for telemetry. the isum current level at maximum load, or idd spike is 36a and this translates to an imon current level of 9a. the imon resistor is 133k and the 9a flowing through the imon resistor results in a 1.2v level at maximum loading of the vr. the overcurrent threshold is 1.5v on the imon pin. based on a 1.2v imon voltage equating to 10 0% loading, the additional 0.3v provided above this level equates to a 25% increase in load current before an ocp fault is detected. the edc or idd spike current is used to set the 1.2v on imon for full load current. so the ocp level is 1.25x the edc or idd spike current level. this additional margin above the edc or idd spike current allows the amd cpu to enter and exit the idd spike performance mode without issue unless the load current is out of line with the idd spike expectation, thus the need for overcurrent protection. when the voltage on the imon pin meets the overcurrent threshold of 1.5v, this triggers an ocp event. within 2s of detecting an ocp event, the cont roller asserts vr_hot_l low to communicate to the amd cpu to throttle back. a fault timer begins counting while imon is at or above the 1.5v threshold. the fault timer lasts 7.5s to 11s and then flags an ocp fault. the controller then tri-states the ac tive channels and goes into shutdown. pgood is taken low and a fa ult flag from this vr is sent to the other vr and it is shutdown within 10s. if the imon voltage drops below the 1.5v threshold prior to the fault timer count finishing, the fault timer is clea red and vr_hot_l is taken high. the ISL62771 also features a way-overcurrent [woc] feature, which immediately takes the controller into shutdown. this protection is also referred to as fast overcurrent protection for short-circuit protection. if the imon current reaches 15a, woc is triggered. active channels are tri-stated and the controller is placed in shutdown and pgood is pulled low. there is no fault timer on the woc fault, the contro ller takes immediate action. the other controller output is also shutdown within 10s. current-balance the controller monitors the isenx pin voltages to determine current-balance protection. if the isenx pin voltage difference is greater than 9mv for 1ms, the controller will declare a fault and latch off. undervoltage if the vsen voltage falls below th e output voltage vid value plus any programmed offsets by -325mv, the controller declares an undervoltage fault. the controller de-asserts pgood and tri-states the power mosfets. overvoltage if the vsen voltage exceeds the ou tput voltage vid value plus any programmed offsets by +325mv, the controller declares an overvoltage fault. the controller de-asserts pgood and turns on the low-side power mosfets. the low- side power mosfets remain on until the output voltage is pulled down below the vid set value. once the output voltage is below this leve l, the lower gate is tri-stated. if the output voltage rises above the overvoltage threshold again, the protection process is repeated. when all power mosfets are turned table 12. tfn truth table tfn, core, nb bits [21,6,7] description 1,0,1 telemetry is in voltage and current mode. therefore, voltage and current are sent for vdd and vddnb domains by the controller. 1,0,0 telemetry is in voltage mode only. only the voltage of vdd and vddnb domains is sent by the controller. 1,1,0 telemetry is disabled. 1,1,1 reserved
ISL62771 26 fn8321.2 september 12, 2013 off. this behavior provides the maximum amount of protection against shorted high-side power mosfets while preventing output ringing below ground. thermal monitor [ntc, ntc_nb] the ISL62771 features two thermal monitors, which use an external resistor network that includes an ntc thermistor to monitor motherboard temperature and alert the amd cpu of a thermal issue. figure 18 shows the basic thermal monitor circuit on the core vr ntc pin. the no rthbridge vr features the same thermal monitor. the controller drives a 30a current out of the ntc pin and monitors the voltage at the pin. the current flowing out of the ntc pin creates a voltage that is compared to a warning threshold of 640mv. when the voltage at the ntc pin falls to this warning threshold or below, the controller asserts vr_hot_l to alert the amd cpu to throttle back load current to stabilize the motherboard temperature. a thermal fault counter begins counting toward a mini mum shutdown time of 100s. the thermal fault counter is an up/down counter, so if the voltage at the ntc pin rises abov e the warning threshold, it will count down and extend the time for a thermal fault to occur. the warning threshold does have 20mv of hysteresis. if the voltage at the ntc pin continues to fall down to the shutdown threshold of 580mv or below, the controller goes into shutdown and triggers a thermal fault. the pgood pin is pulled low and tri-states the power mosfet s. a fault on either side will shutdown both vrs. as the board temperature rises, the ntc thermistor resistance decreases and the voltage at the ntc pin drops. when the voltage on the ntc pin drops below the over-temperature trip threshold, then vr_hot is pulled low. the vr_hot signal is used to change the cpu operation an d decrease power consumption. with the reduction in power cons umption by the cpu, the board temperature decreases and the nt c thermistor voltage rises. once the over-temperature threshold is tripped and vr_hot is taken low, the over-temperature threshold changes to the reset level. the addition of hysteresis to the over-temperature threshold prevents nuisance trips. once both pin voltages exceed the over-temperature reset thresh old, the pull-down on vr_hot is released. the signal changes state and the cpu resumes normal operation. the over-tempe rature threshold returns to the trip level. table 13 summarizes the fault protections. fault recovery all of the previously described fa ult conditions can be reset by bringing enable low or by bringing vdd below the por threshold. when enable and vdd return to their high operating levels, the controller resets the faults and soft-start occurs. interface pin protection the svc and svd pins feature protection diodes, which must be considered when removing power to vdd and vddio, but leaving it applied to these pins. figure 19 shows the basic protection on the pins. if svc and/or svd are powered but vdd is not, leakage current will flow from these pins to vdd. ntc r ntc v ntc - + 30a internal to ISL62771 figure 18. circuitry associated with the thermal monitor feature of the ISL62771 r s monitor r +v r p warning 640mv shutdown 580mv vr_hot_l table 13. fault protection summary fault type fault duration before protection protection action fault reset overcurrent 7.5s to 11.5s pwm tri-state, pgood latched low enable toggle or vdd toggle phase current unbalance 1ms way-overcurrent (1.5xoc) immediately undervoltage -325mv pgood latched low. pwm tri-state. overvoltage +325mv pgood latched low. actively pulls the output voltage to below vid value, then tri-state. ntc thermal 100s min pgood latched low. pwm tri-state. svc, svd internal to ISL62771 figure 19. protection devices on the svc and svd pins gnd vdd
ISL62771 27 fn8321.2 september 12, 2013 key component selection inductor dcr current-sensing network figure 20 shows the inductor dcr current-sensing network for a 2-phase solution. an inductor current flows through the dcr and creates a voltage drop. each inductor has two resistors in r sum and r o connected to the pads to a ccurately sense the inductor current by sensing the dcr voltage drop. the r sum and r o resistors are connected in a summing network as shown, and feed the total current information to the ntc network (consisting of r ntcs , r ntc and r p ) and capacitor c n . r ntc is a negative temperature coefficient (ntc) thermistor, used to temperature compensate the inductor dcr change. the inductor output side pads are electrically shorted in the schematic but have some parasi tic impedance in actual board layout, which is why one cannot simply short them together for the current-sensing summing network. it is recommended to use 1 ~10 r o to create quality signals. since r o value is much smaller than the rest of the current sensing circuit, the following analysis ignores it. the summed inductor current information is presented to the capacitor c n . equations 13 thru 17 describe the frequency domain relationship between inductor total current i o (s) and c n voltage v cn (s): where n is the number of phases. transfer function a cs (s) always has unity gain at dc. the inductor dcr value increases as the wi nding temperature increases, giving higher reading of the inductor dc current. the ntc r ntc value decrease as its temperature decreases. proper selection of r sum , r ntcs , r p and r ntc parameters ensures that v cn represents the inductor total dc current over the temperature range of interest. there are many sets of parameters that can properly temperature-compensate the dcr change. since the ntc network and the r sum resistors form a voltage divider, v cn is always a fraction of the inductor dcr voltage. it is recommended to have a higher ratio of v cn to the inductor dcr voltage so the droop circuit has a higher signal level to work with. a typical set of parameters that provide good temperature compensation are: r sum = 3.65k , r p =11k , r ntcs = 2.61k and r ntc = 10k (ert-j1vr103j). the ntc network parameters may need to be fine tuned on actual boards. one can apply full load dc current and record the output voltage reading immediately; then record the ou tput voltage reading again when the board has reached the thermal steady state. a good ntc network can limit the output voltag e drift to within 2mv. it is recommended to follow the intersil evaluation board layout and current sensing network parameters to minimize engineering time. v cn (s) also needs to represent real-time i o (s) for the controller to achieve good transient response. transfer function a cs (s) has a pole sns and a zero l . one needs to match l and sns so a cs (s) is unity gain at all frequencies. by forcing l equal to sns and solving for the solution, equation 18 gives cn value. for example, given n = 2, r sum = 3.65k , r p = 11k , r ntcs =2.61k , r ntc = 10k , dcr = 0.88m and l = 0.36h, equation 18 gives c n = 0.294f. assuming the compensator design is correct, figure 21 shows the expected load transient response waveforms if c n is correctly selected. when the load current i core has a square change, the output voltage v core also has a square response. if c n value is too large or too small, v cn (s) does not accurately represent real-time i o (s) and worsens the transient response. figure 22 shows the load transient response when c n is too small. v core sags excessively upon load insertion and may create a system failure. figure 23 shows the transient response when c n is too large. v core is sluggish in drooping to its final value. there is excessive overshoot if load insertion occurs during this time, which may negatively affect the cpu reliability. cn r ntcs r ntc r p dcr l r sum r o phase2 i o dcr l phase1 r o r sum ri i sum+ i sum- vcn + - figure 20. dcr current-sensing network v cn s () r ntcnet r ntcnet r sum n -------------- - + ------------------------------------------ dcr n ------------- ?? ?? ?? ?? ?? i o s () a cs s () = (eq. 13) r ntcnet r ntcs r ntc + () r p r ntcs r ntc r p ++ ---------------------------------------------------- = (eq. 14) a cs s () 1 s l ------ - + 1 s sns ------------ - + ---------------------- - = (eq. 15) l dcr l ------------- = (eq. 16) sns 1 r ntcnet r sum n -------------- - r ntcnet r sum n -------------- - + ------------------------------------------ c n -------------------------------------------------------- = (eq. 17) c n l r ntcnet r sum n -------------- - r ntcnet r sum n -------------- - + ------------------------------------------ dcr -------------------------------------------------------------- - = (eq. 18)
ISL62771 28 fn8321.2 september 12, 2013 figure 24 on page 28 shows the output voltage ring-back problem during load transient response. the load current i o has a fast step change, but the inductor current i l cannot accurately follow. instead, i l responds in first-order system fashion due to the nature of the current loop. the esr and esl effect of the output capacitors makes the output voltage v o dip quickly upon load current change. however, the controller regulates v o according to the droop current i droop , which is a real-time representation of i l ; therefore, it pulls v o back to the level dictated by i l , causing the ring-back problem. this phenomenon is not observed when the output capacitor has very low esr and esl, as is the case with all ceramic capacitors. figure 25 shows two optional ci rcuits for reduction of the ring-back. c n is the capacitor used to match the inductor time constant. it usually takes the parallel of two (or more) capacitors to get the desired value. figure 25 shows that two capacitors (c n.1 and c n.2 ) are in parallel. resistor r n is an optional component to reduce the v o ring-back. at steady state, c n.1 +c n.2 provides the desired c n capacitance. at the beginning of i o change, the effective capacitance is less because r n increases the impedance of the c n.1 branch. as figure 22 shows, v o tends to dip when c n is too small, and this effect reduces the v o ring-back. this effect is more pronounced when c n.1 is much larger than c n.2 . it is also more pronounced when r n is bigger. however, the presence of r n increases the ripple of the v n signal if c n.2 is too small. it is recommended to keep c n.2 greater than 2200pf. r n value usually is a few ohms. c n.1 , c n.2 and r n values should be determined through tuni ng the load transient response waveforms on an actual board. r ip and c ip form an r-c branch in parallel with r i , providing a lower impedance path than r i at the beginning of i o change. r ip and c ip do not have any effect at steady state. through proper selection of r ip and c ip values, i droop can resemble i o rather than i l , and v o will not ring back. the recommended value for r ip is 100 . c ip should be determined through tuning the load transient response waveforms on an actual board. the recommended range for c ip is 100pf~2000pf. however, it sh ould be noted that the r ip -c ip branch may distort the i droop waveform. instead of being triangular as the real inductor current, i droop may have sharp spikes, which may adversely affect i droop average value detection and therefore may affect ocp accuracy. user discretion is advised. figure 21. desired load tr ansient response waveforms o i v o figure 22. load transient response when c n is too small o i v o figure 23. load transient response when c n is too large o i v o figure 24. output voltage ring-back problem o i v o l i ring back figure 25. optional circuits for ring-back reduction cn.2 rntcs rntc rp ri isum+ isum- rip cip optional vcn cn.1 rn optional + -
ISL62771 29 fn8321.2 september 12, 2013 resistor current-sensing network figure 26 shows the resistor current-sensing network for a 2-phase solution. each inductor has a series current sensing resistor, r sen . r sum and r o are connected to the r sen pads to accurately capture the inductor current information. the r sum and r o resistors are connected to capacitor c n . r sum and c n form a filter for noise attenuation. equations 19 thru 21 give the v cn (s) expression. transfer function a rsen (s) always has unity gain at dc. current-sensing resistor r sen value does not have significant variation over-temperature, so there is no need for the ntc network. the recommended values are r sum = 1k and c n = 5600pf. overcurrent protection refer to equation 2 on page 17 and figures 20, 24 and 26; resistor r i sets the i sum current which is proportional to droop current and imon current. tables 1 and 2 show the internal ocp threshold based on the imon pin voltage. since the r i resistor impacts both the droop current and the imon current, fine adjustments to i droop will require changing the r comp resistor. for example, the ocp threshold is 1.5v on the imon pin, which equates to an imon current of 11.25a using a 133k imon resistor. the corresponding isum current is 45a, which results in an i droop of 56.25a. at full load current, i omax , the isum current is 36a and the resulting i droop is 45a. the ratio of the isum current at ocp relative to full load is 1.25. therefore, the ocp current trip level is 25% higher than the full load current. for inductor dcr sensing, equation 22 gives the dc relationship of v cn (s) and i o (s): substitution of equation 22 into equation 2 gives equation 23: therefore: substitution of equation 14 and application of the ocp condition in equation 24 gives equation 25: where i omax is the full load current and i droopmax is the corresponding droop current. for example, given n = 2, r sum = 3.65k , r p = 11k , r ntcs = 2.61k , r ntc = 10k , dcr = 0.88m , i omax = 50a and i droopmax = 45a. equation 25 gives r i = 466 . for resistor sensing, equation 26 gives the dc relationship of v cn (s) and i o (s). substitution of equation 26 into equation 2 gives equation 27: therefore: substitution of equation 28 and application of the ocp condition in equation 24 gives equation 29: where i omax is the full load current and i droopmax is the corresponding droop current. for example, given n = 2, r sen =1m , i omax = 50a and i droopmax = 45a, equation 29 gives r i = 694 . load line slope see figure 13 for load-line implementation. figure 26. resistor current-sensing network cn dcr l r sum r o phase2 i o dcr l phase1 r o r sum ri i sum+ i sum- vcn rsen rsen + - v cn s () r sen n ------------- i o s () a rsen s () = (eq. 19) a rsen s () 1 1 s sns ------------ - + ---------------------- - = (eq. 20) rsen 1 r sum n -------------- - c n ---------------------------- - = (eq. 21) v cn r ntcnet r ntcnet r sum n -------------- - + ------------------------------------------ dcr n ------------- ?? ?? ?? ?? ?? i o = (eq. 22) i droop 5 4 -- - 1 r i ----- r ntcnet r ntcnet r sum n -------------- - + ------------------------------------------ dcr n ------------- i o = (eq. 23) r i 5 4 -- - r ntcnet dcr i o nr ntcnet r sum n -------------- - + ?? ?? i droop --------------------------------------------------------------------------------- - = (eq. 24) r i 5 4 -- - r ntcs r ntc + () r p r ntcs r ntc r p ++ ---------------------------------------------------- dcr i omax n r ntcs r ntc + () r p r ntcs r ntc r p ++ ---------------------------------------------------- r sum n -------------- - + ?? ?? ?? i droopmax ---------------------------------------------------------------------------------------------------------------------------- - = (eq. 25) v cn r sen n ------------- i o = (eq. 26) i droop 5 4 -- - 1 r i ----- r sen n ------------- i o = (eq. 27) r i 5 4 -- - r sen i o ni droop --------------------------- = (eq. 28) r i 5 4 -- - r sen i omax ni droopmax -------------------------------------- = (eq. 29)
ISL62771 30 fn8321.2 september 12, 2013 for inductor dcr sensing, substitution of equation 23 into equation 3 gives the load-line slope expression in equation 30: for resistor sensing, substitution of equation 27 into equation 3 gives the load line slope expression in equation 31: substitution of equation 24 and rewriting equation 30, or substitution of equation 28 and rewriting equation 31, gives the same result as in equation 32: one can use the full-load condition to calculate r droop . for example, given i omax = 50a, i droopmax = 45a and ll = 2.1m , equation 32 gives r droop = 2.33k . it is recommended to start with the r droop value calculated by equation 32 and fine-tune it on the actual board to get accurate load-line slope. one should record the output voltage readings at no load and at full load for load -line slope calculation. reading the output voltage at lighter load instead of full load will increase the measurement error. compensator figure 21 shows the desired load transient response waveforms. figure 27 shows the equivalent circuit of a voltage regulator (vr) with the droop function. a vr is equivalent to a voltage source (= vid) and output impedance z out (s). if z out (s) is equal to the load-line slope ll, i.e., a constant output impedance, then in the entire frequency range, v o will have a square response when i o has a square change. intersil provides a microsoft excel-based spreadsheet to help design the compensator and the cu rrent sensing network so that vr achieves constant output impedance as a stable system. a vr with active droop function is a dual-loop system consisting of a voltage loop and a droop loop, which is a current loop. however, neither loop alone is sufficient to describe the entire system. the spreadsheet shows two loop gain transfer functions, t1(s) and t2(s), that describe the entire system. figure 28 conceptually shows t1(s) measurement set-up , and figure 29 conceptually shows t2(s) measurement set-up. the vr senses the inductor current, multiplies it by a gain of the load-line slope, adds it on top of the sensed output voltage, and then feeds it to the compensator. t1 is measured af ter the summing node, and t2 is measured in the voltage loop before the summing node. the spreadsheet gives both t1(s) and t2(s) plots. however, only t2(s) can actually be measured on an ISL62771 regulator. t1(s) is the total loop gain of the voltage loop and the droop loop. it always has a higher crossover frequency than t2(s), therefore has a higher impact on system stability. t2(s) is the voltage loop gain with closed droop l oop, thus having a higher impact on output voltage response. design the compensator to get stable t1(s) and t2(s) with sufficient phase margin and an output impedance equal to or smaller than the load-line slope. current balancing refer to figures 14 through 20 for information on current balancing. the ISL62771 achieves current balancing through matching the isen pin voltages. r isen and c isen form filters to remove the switching ripple of the phase node voltages. it is recommended to use a rather long r isen c isen time constant, such that the isen voltages have minimal ripple and represent ll v droop i o ------------------ - 5 4 -- - r droop r i ------------------- r ntcnet r ntcnet r sum n -------------- - + ------------------------------------------ dcr n ------------- == (eq. 30) ll v droop i o ------------------ - 5 4 -- - r sen r droop nr i --------------------------------------- == (eq. 31) r droop i o i droop ---------------- ll = (eq. 32) figure 27. voltage regulator equivalent circuit o i v o vid z out (s) = ll load vr figure 28. loop gain t1(s) measurement set-up q2 q1 l i o c out v o v in gate driver comp mod. load line slope ea vid channel b channel a excitation output isolation transformer 20 loop gain = channel b channel a network analyzer + + + - figure 29. loop gain t2(s) measurement set-up q2 q1 l i o c o v o v in gate driver comp mod. load line slope ea vid channel b channel a excitation output isolation transformer 20 loop gain = channel b channel a network analyzer + + + -
ISL62771 31 fn8321.2 september 12, 2013 the dc current flowing through the inductors. recommended values are r s = 10k and c s = 0.22f. thermal monitor component selection the ISL62771 features two pins, ntc and ntc_nb, which are used to monitor motherboard temperature and alert the amd cpu if a thermal issue arises. the basic function of this circuitry is outlined in the ?thermal monitor [ntc, ntc_nb]? on page 26. figure 30 shows the basic configuration of the ntc resistor, r ntc , and offset resistor, r s , used to generate the warning and shutdown voltages at the ntc pin. as the board temperature rises, the ntc thermistor resistance decreases and the voltage at the ntc pin drops. when the voltage on the ntc pin drops below the thermal warning threshold of 0.64v, then vr_hot_l is pulled low. when the amd cpu detects vr_hot_l has gone low, it will begin throttling back load current on both outputs to reduce the board temperature. if the board temperature continues to rise, the ntc thermistor resistance will drop further and the voltage at the ntc pin could drop below the thermal shutdown threshold of 0.58v. once this threshold is reached, the ISL62771 shuts down both core and northbridge vrs indicating a ther mal fault has occurred prior to the thermal fault counter triggering a fault. selection of the ntc thermistor can vary depending on how the resistor network is configured. th e equivalent resistance at the typical thermal warning threshold voltage of 0.64v is defined in equation 33. the equivalent resistance at the typical thermal shutdown threshold voltage of 0.58v required to shutdown both outputs is defined in equation 34. the ntc thermistor value correlates to the resistance change between the warning and shutdown thresholds and the required temperature change. if the warning level is designed to occur at a board temperature of +100c and the thermal shutdown level at a board temperature of +105c, th en the resistance change of the thermistor can be calculated. for example, a panasonic ntc thermistor with b = 4700 has a resi stance ratio of 0.03939 of its nominal value at +100c and 0.03308 of its nominal value at +105c. taking the required re sistance change between the thermal warning threshold and the shutdown threshold and dividing it by the change in resi stance ratio of the ntc thermistor at the two temperatures of interest, the required resistance of the ntc is defined in equation 35. the closest standard thermistor to the value calculated with b = 4700 is 330k . the ntc thermistor part number is ertj0ev334j. the actual resistan ce change of this standard thermistor value between the warning threshold and the shutdown threshold is calculated in equation 36. since the ntc thermist or resistance at +105c is less than the required resistance from equation 38, additional resistance in series with the thermistor is requ ired to make up the difference. a standard resistor, 1% toleranc e, added in series with the thermistor will increase the voltage seen at the ntc pin. the additional resistance required is calculated in equation 37. the closest, standard 1% tolerance resistor is 8.45k . the ntc thermistor is placed in a hot spot on the board, typically near the upper mosfet of channe l 1 of the respective output. the standard resistor is pl aced next to the controller. layout guidelines pcb layout considerations power and signal layers placement on the pcb as a general rule, power layers should be close together, either on the top or bottom of the board, with the weak analog or logic signal layers on the opposite side of the board. the ground-plane layer should be adjacent to the signal layer to provide shielding. component placement there are two sets of critical components in a dc/dc converter; the power components and the small signal components. the power components are the most critical because they switch large amount of energy. the small signal components connect to sensitive nodes or supply critic al bypassing current and signal coupling. the power components should be placed first and these include mosfets, input and output capacitors, and the inductor. it is important to have a symmetrical layout for each power train, preferably with the controller located equidistant from each power train. symmetrical layout allows heat to be dissipated equally across all power trains. keeping the distance between the power train and the control ic short helps keep the gate drive traces short. these drive signals include the lgate, ugate, pgnd, phase and boot. ntc r ntc 30a internal to ISL62771 figure 30. thermal monitor feature of the ISL62771 r s monitor r +v warning 640mv shutdown 580mv vr_hot_l 330k 8.45k 0.64v 30 a --------------- - 21.3k = (eq. 33) 0.58v 30 a --------------- - 19.3k = (eq. 34) 21.3k 19.3k ? () 0.03939 0.03308 ? () ----------------------------------------------------- - 317k = (eq. 35) 330k 0.03939 ? () 330k 0.03308 ? () ? 2.082k = (eq. 36) 19.3k 10.916k ? 8.384k = (eq. 37)
ISL62771 32 fn8321.2 september 12, 2013 when placing mosfets, try to keep the source of the upper mosfets and the drain of the lower mosfets as close as thermally possible (see figure 31). input high-frequency capacitors should be placed close to the drain of the upper mosfets and the source of the lower mosfets. place the output inductor and output capacitors between the mosfets and the load. high-frequency output decoupling capacitors (ceramic) should be placed as close as possible to the decoupling target (microprocessor), making use of the shortest connection paths to any internal planes. place the components in such a way that the area under the ic has less noise traces with high dv/dt and di/dt, such as gate signals and phase node signals. table 14 shows layout considerations for the ISL62771 controller by pin. figure 31. typical power component placement inductor vias to ground plane vin vout phase node gnd output capacitors low-side mosfets input capacitors schottky diode high-side mosfets table 14. layout considerations for the ISL62771controller ISL62771 pin symbol layout guidelines bottom pad gnd connect this ground pad to the ground plane through a low impedance path. a minimum of 5 vias are recommended to connect this pad to the in ternal ground plane layers of the pcb 1 ntc_nb the ntc thermistor must be placed close to the th ermal source that is monitored to determine northbridge thermal throttling. placement at the hottest spot of th e northbridge vr is recomme nded. additional standard resistors in the resistor network on this pin should be placed near the ic. 2 imon_nb place the imon_nb resistor close to this pin and make keep a tight gnd connection. 3 svc use good signal integrity practi ces and follow amd recommendations. 4 vr_hot_l follow amd recommendations. placement of the pull-up resistor near the ic is recommended. 5 svd use good signal integrity practi ces and follow amd recommendations. 6 vddio use good signal integrity prac tices and follow amd recommendations. 7 svt use good signal integrity practi ces and follow amd recommendations. 8 enable use good signal integrity practices. 9 pwrok use good signal integrity prac tices and follow amd recommendations. 10 imon place the imon resistor close to this pin and make keep a tight gnd connection. 11 ntc the ntc thermistor must be placed close to the ther mal source that is monitored to determine core thermal throttling. placement at the hottest spot of the core vr is recommended. additional standard resistors in the resistor network on this pin should be placed near the ic.
ISL62771 33 fn8321.2 september 12, 2013 12 isen2 each isen pin has a capacitor (c isen ) decoupling it to vsumn and then through another capacitor (c vsumn ) to gnd. place cisen capacitors as close as possible to the controller and keep the following loops small: 1. any isen pin to another isen pin 2. any isen pin to gnd the red traces in the following drawing show the loops to be minimized. 13 isen1 14 isump place the current sensing circuit in general proximity of the controller. place capacitor cn very close to the controller. place the ntc thermistor next to core vr channel 1 indu ctor so it senses the inductor temperature correctly. each phase of the power stage sends a pair of vsum p and vsumn signals to the controller. run these two signals traces in parallel fashion with decent width (>20mil). important: sense the inductor current by routing the sensing circuit to the inductor pads. if possible, route the traces on a different layer from the inductor pad layer an d use vias to connect the traces to the center of the pads. if no via is allowed on the pad, consider routing th e traces into the pads from the inside of the inductor. the following drawings show the two preferre d ways of routing current sensing traces. 15 isumn 16 vsen place the filter on these pins in close proximity to the controller for good coupling. 17 rtn 18 fb place the compensation components in general proximity of the controller. 19 comp 20 pgood no special consideration. 21 boot1 use a wide trace width (>30mil). avoid routing any sensit ive analog signal traces clos e to or crossing over this trace. 22 ugate1 these two signals should be routed together in parallel. each trace should have sufficient width (>30mil). avoid routing these signals near sensitive analog signal traces or crossing over them. routing phase1 to the core vr channel 1 high-side mosfet so urce pin instead of a general connection to phase1 copper is recommended for better performance. 23 phase1 24 lgate1 use sufficient trace width (>30mil). avoid routing this signal near any sensitive analog signal traces or crossing over them. table 14. layout considerations for the ISL62771controller (continued) ISL62771 pin symbol layout guidelines v o isen2 isen1 l2 l1 risen risen phase1 phase2 ro ro gnd cisen cisen cvsumn vsumn inductor current-sensing traces vias inductor current-sensing traces
ISL62771 34 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8321.2 september 12, 2013 for additional products, see www.intersil.com/en/products.html 25 vdd a high quality, x7r dielectric mlcc capacitor is reco mmended to decouple this pin to gnd. place the capacitor in close proximity to the pin with the filter resistor nearby the ic. 26 vddp a high quality, x7r dielectric mlcc capacitor is reco mmended to decouple this pin to gnd. place the capacitor in close proximity to the pin. 27 lgate2 use sufficient trace width (>30mil). avoid routing this signal near any sensitive analog signal traces or crossing over them. 28 phase2 these two signals should be routed together in parallel. each trace should have sufficient width (>30mil). avoid routing these signals near sensitive analog signal traces or crossing over them. routing phase2 to the core vr channel 2 high-side mosfet so urce pin instead of a general connection to phase2 copper is recommended for better performance. 29 ugate2 30 boot2 use a wide trace width (>30mil). avoid routing any sensit ive analog signal traces clos e to or crossing over this trace. 31 boot_nb use a wide trace width (>30mil). avoid routing any sensit ive analog signal traces clos e to or crossing over this trace. 32 ugate_nb these two signals should be routed together in parallel. each trace should have sufficient width (>30mil). avoid routing these signals near sensitive analog signal trac es or crossing over them. routing phase_nb to the northbridge vr high-side mosfet source pin instead of a general connection to phase_nb copper is recommended for better performance. 33 phase_nb 34 lgate_nb use sufficient trace width (>30mil). avoid routing this signal near any sensitive analog signal traces or crossing over them. 35 pgood_nb no special consideration. 36 comp_nb place the compensation components in general proximity of the controller. 37 fb_nb 38 vsen_nb place the filter on this pin in close proximity to the controller for good coupling. 39 isumn_nb place the current sensing circuit in general proximity of the controller. place capacitor cn very close to the controller. place the ntc thermistor next to northbridge vr channe l 1 inductor so it senses the inductor temperature correctly. each phase of the power stage sends a pair of vsump and vsumn signals to the controller. run these two signals traces in parallel fa shion with decent width (>20mil). important: sense the inductor current by routing the sensing circuit to the inductor pads. if possible, route the traces on a different layer from the inductor pad layer an d use vias to connect the traces to the center of the pads. if no via is allowed on the pad, consider routing th e traces into the pads from the inside of the inductor. the following drawings show the two preferre d ways of routing current sensing traces. 40 isump_nb table 14. layout considerations for the ISL62771controller (continued) ISL62771 pin symbol layout guidelines inductor current-sensing traces vias inductor current-sensing traces
ISL62771 35 fn8321.2 september 12, 2013 about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change september 12, 2013 fn8321.2 ordering information table on page 10: ch anged irtz part temperature from -40c to +85c to -40c to +100c. page 15, channel configuration section, removed ?as will connecting isen1_nb to +5v will disable the northbridge vr output.? changed temperature -40c to +85c to -40c to +100c throughout the datasheet. december 18, 2012 fn8321.1 changed agnd symbols to gnd symbols in figures 3 thru 5 and pin 12/13 drawing in the layout guidelines table. the ic has a single gnd connec tion which all signals are referenced. november 19, 2012 fn8321.1 typo on page 10 in the pin description for comp_nb pin. changed "slew rate" to "switching frequency". the part description in all other places indicated that the slew rate is fixed and the switching frequency is set by the comp_nb resistor. corrected part marking in ?ordering information? on page 10. june 13, 2012 fn8321.0 initial release
ISL62771 36 fn8321.2 september 12, 2013 package outline drawing l40.5x5 40 lead thin quad flat no-lead plastic package rev 1, 9/10 typical recommended land pattern detail "x" top view bottom view side view located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.27mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: (40x 0.60) 0.00 min 0.05 max (4x) 0.15 index area pin 1 pin #1 index area c seating plane base plane 0.08 see detail ?x? c c 5 6 a b b 0.10 m a c c 0.10 // 5.00 5.00 3.50 5.00 0.40 4x 3.60 36x 0.40 3.50 0.20 40x 0.4 0 .1 0.750 0.050 0.2 ref (40x 0.20) (36x 0.40 b package outline jedec reference drawing: mo-220whhe-1 7. 6 4

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